The aim is to complete the following:
- B6700 software restoration - recover ALGOL, ESPOL, MCP and Intrinsics.
- B6700 emulator - goal is to be able to run B6700 software on a modern machine
- B-series product range - compile a comprehensive description of the various models and their differences
- B6700 front-panel replica - along the lines of the B205 project design and construct a replica of a main processor control panel.
- Burroughs machines in Tasmania - Discover and identify - UTAS had both a B6700 and B6800(?) in the Computing Centre and a B1700 in Administration. Savings Bank of Tasmania (SBT) had a B6800 (to be confirmed) and later an A-series system (Unisys).
The University of Tasmania Computing Centre operated a Burroughs B6700 mainframe as a replacement for the previously long-running Elliott 503 jointly operated by the Hydro Electric Commission and University.
Known B6700 installations in Australasia
Photo by Ralph K
, Monash University B6700, circa early 1980s
Product range (marchitecture)
This is an attempt to reconcile various statements made about Burroughs "large systems" models which were released, renamed, superceded or ommitted and so on. For example, the wikipedia page
does not mention the B5900 despite the linked article at the bottom of the page to a long description from the "father of the B5900 System
"marchitecture" - the table below shows the naming scheme seemingly defined by how the machines were released and marketed. The "series' groupings do not reflect the architectural lineage of these machines.
||Notes (many taken from Jack Hoaroots)
|B5000|| || || ||
||Hardware implementation problems, replaced with B5500
| ||B5500|| || ||
||Essentially the B5000 with disk instead of drum and improved software.
| ||B6500|| || ||
||1968 or 1969
||Like the B5000, had reliability problems and quickly replaced with the B6700. All were field upgraded to B6700s
| ||B8500|| || || ||1968 - 1970||Never delivered due to engineering problems|
| || || || || ||1970||Last B5500 manufactured|
| || || B5700|| || ||1970|| |
| || || B6700|| ||
||Max of 1M word (48-bit word + 4 tag bits), 6MBytes memory
1 - 3 CPUs and 1-2 I/O Processors
All B6500s were field upgraded to B6700 to correct engineering problems with the B6500
| || || B7700|| ||
||Initially up to 4 CPUs and 2 I/O processors but later up to 8 CPUs
| || || ||B6800||
||high performance, lower cost version of the B6700 with a new memory architecture (so-called Global Memory Architecture supporting multi-processor operation)
| || || ||B7800 ||
| || || || ||B5900
||First E-mode implementation (consolidation of all the previous models instruction sets) implemented loadable microcode. Had 4 Display registers D, D. D, D[LL], where LL refers to the current lexical level.
| || || || ||B6900
||Last of the "E-mode" machines implemented in hardware, 99% compatible with the E-mode design.
| || || || ||B7900
| || || ||A-series||
Product range (actual)
this section needs much more detail and a better layout
The "marchitecture" table above attempts to make sense of the historical numbering convention from a marketing or customer perspective.
The actual implementation and packing or bundling differences are described in this section.
From a implementation perspective the following is what actually existed in terms of hardware/software differences (as explained by Paul Kimpel comp.arch):
B5500 1964 until 1970
B5700 1970 final marketed version of the B5000/B5500 architecture - A B5500 combined with the B6500 datacom processor (DCP) and the ability to attach B6500 memory modules to the drum interfaces.
DMCP (Disk MCP), TS-MCP (time-sharing MCP) were distinct implementations. The B5700 was simply a renamed B5500 however the peripherals shipped with the system were changed and the DCP was from the B6500.
B6500 started 1965, released 1969, then quickly replaced due to engineering problems with the fixed (re-labelled) B6700
B6700 / B7700 (previously B6500/B7500) substantially different design from the B5000/B5500/B5700 - different instruction set, descriptors and control word formats, physical and virtual address space limits increased dramatically, completely new character (string) processing system, and a re-designed MCP (now unified as a single implementation for batch and time-sharing).
B6800/7800/B5900/B6900/B7900 - technology refinements of the B6700/B7700 family.
B6700 Display Panel
The B6700 was designed in an era when the clock speed was low enough, and the need great enough that the internal state of the system was exposed to operators and users of the system via an array of lights on a panel, usually known as a front-panel, display panel, or engineers panel. The B6700 operated on a clock cycle of 2.5MHz or 5.0MHz with instructions taking several cycles. Memory cycle time was one of 0.5 usec, 1.2 usec or 1.5 usec.
The B6700 Display Panel is a somewhat complex arrangement of overlays as most of the panels above are shared between CPU and IO processors and different control groups (Memory Controller, Arithmetic Controller, Interrupt Controller etc). The Display Panel (DP) consists of switches, lights, and combined switch-lights. Most of the bits within registers are combined switch-lights so the state of a register bit can be both seen and manipulated from the DP. Apparently, when operators were bored and the machine was hopefully(!) not busy a popular game was to play russian-roulette, pick a random register bit, flip its state and see how many times bits can be changed before the machine crashed or DS'd (discontinued) a job.
Panel A shows the important programmer visible registers of the selected CPU. From top to bottom of Panel A is:
- P register (51-bits) -
- C register (51-bits) - temporary register for some operations and memory cycle states
- A register (51-bits) - this is the top-of-stack register
- B register (51-bits) - this the second word in the stack
- X register (51-bits) - X is an extension word for A when processing double-precision operands.
- Y register (51-bits) - Y is an extension word for B
when processing double-precision operands.
An interesting feature of Panel A due to its display of the TOS registers, when the CPU was idle the MCP arranged the bit pattern to appear in the TOS registers to display a large letter B (for Burroughs) as can be seen in the picture above. This letter "B" would flicker on and off (replaced with other patterns of lights) as the MCP switched between idle and busy states.
- Exact installation, commission and de-commissioning dates for the UTAS B6700 to be discovered
Burroughs Model III B6700 processor with vector mode hardware, 196k words of main store, 4 pack drives etc with MCP Version 11.8 - from: Pascal User Group Newsletter (PUGN) #6, Letter from AJH Sale, dated 8-Nov-1976 - as the machine was commissioned in late 1975 this configuration is likely close to what was initially delivered.
- Configuration details of the UTAS B6700 still to be determined.
- Due to the high cost of Burroughs memory, memory expansion for the B6700 was undertaken using a local design. The memory expansion took the machine to its maximum memory (1MW or 6MB)
- At the time of installation the UTAS B6700 may have been the largest machine installed in Tasmania - compare with the State Government Unisys 1108 installed sometime in the 1970s(?)
- Professor Sale and colleagues constructed a B6700 Pascal compiler which was later sold to Burroughs as their official Pascal compiler
- At some stage the B6700 was upgraded to a later model, either a B6800 or B6900
B5700/B6700 Cactus stack
Contacts and contributors
- Development history of the B5900
- Stories about the B5000 and people who were there, Richard Waychoff (includes detail on the Burroughs ALGOL compiler and in particular STREAM procedures)
- Burroughs B5000 Descriptor
- The Burroughs B 5000 Conference 6 September 1985, Marina Del Ray Hotel
- Segment Sizes and Lifetimes in ALGOL 60 Programs, AP Batson and RE Brundage, University of Virginia, CACM January 1977
- The architecture of the Burroughs B5000 - 20 years Later and Still Ahead of the Times? published in 1982